1. Field of the Invention
The present invention relates to computer systems managing large amounts of input/output data, such as internetwork controllers and the like; and particularly to an architecture optimized for bridging, routing, and gateway internetwork functions serving a plurality of different types of networks.
2. Description of Related Art
Internetwork devices, such as bridges, routers, and gateways, often cause a significant bottleneck when communicating data through networks. The processing resources available at the internetwork device has a direct impact on the latency of messages being communicated among the networks. When there are a number of high speed networks connected to a single internetwork device, the processing resources of the internetwork device can be easily overwhelmed.
Techniques for managing the large amounts of I/0 for such internetwork devices include providing a very large memory which can accumulate a lot of I/O data while the internetwork processor executes time consuming procedures that may prevent it from routing a particular packet of data, and increasing the processing power of the internetwork processor.
For high throughput systems, a very large memory can be quite expensive. Similarly, techniques involving multiple processors or very high performance processors that manage the internetworking functions are also expensive. Furthermore, contention between the I/O data transfers to and from the memory and accesses by the processor to the memory limit the effectiveness of increasing memory size or processing power.
Accordingly, there is a need for an architecture for managing large amounts of I/O, such as required in internetwork devices, which significantly increases the bandwidth of the internetwork device.